DS90UH948TNKDRQ1 WQFN64 inventory clearing price discount
explain
DS90UH948-Q1 is an FPD-Link III deserializer. When used with DS90UH949A/949/947-Q1 serializer, it can convert single channel or dual channel FPD-Link III streams to FPD-Link (OpenLDI) interface format. The deserializer can run on 50 Ω single ended coaxial or 100 Ω differential shielded twisted pair (STP) cable with cost efficiency. It can recover data from a single or dual channel FPD-Link III serial stream, and then convert it to a dual pixel FPD-Link (8 LVDS data channels+clock). It can support up to 2K (2048x1080) video resolution (24 bit color depth). This provides a bridge between HDMI capable sources, such as CPUs, to connect to existing LVDS displays or application processors.
FPD-Link III interface supports video and audio data transmission and full duplex control (including I2C and SPI communication) through the same differential link. The integration of video data and control through two differential pairs can reduce the size and weight of the interconnect and simplify the system design. Electromagnetic interference (EMI) is minimized by using low voltage differential signaling, data exchange, and random generation. In backward compatibility mode, the device can support up to WXGA and 720p resolution (24 bit color depth) on a single differential link.
The device will automatically detect FPD-Link III channels and provide a clock alignment and offset compensation function without any special training mode. This ensures that the phase offset is within tolerance when there are mismatches in interconnecting circuits (e.g. PCB wiring), differences in cable pair lengths, and connector imbalance.
characteristic
Meet the requirements of automobile application
The following results comply with AEC Q100 standard:
Device temperature level 2: ambient operating temperature range from - 40 ℃ to+105 ℃
Support pixel clock frequency up to 192 MHz, and achieve resolution up to 2K (2048x1080) (24 bit color depth)
Single or dual channel FPD-Link III interface with offset compensation capability
Single or dual channel OpenLDI (LVDS) transmitter
Single channel: up to 96MHz pixel clock
Dual channel: up to 192MHz pixel clock
Configurable 18 bit RGB or 24 bit RGB
Integrated HDCP cipher engine with on-chip key storage
Support HDCP repeater application
Four channel high-speed GPIO (up to 2Mbps per channel)
Adaptive reception equalization
At 1.7GHz, channel insertion loss compensation is up to – 15.3dB
Provide automatic temperature and cable aging compensation
SPI control interface speed up to 3.3Mbps
I2C with 1Mbps fast mode enhanced version (master/slave)
Image enhancement (white balance and jitter)
Support 7.1 multiple I2S (4 data) channels
DS90UH948-Q1 is an FPD-Link III deserializer. When used with DS90UH949A/949/947-Q1 serializer, it can convert single channel or dual channel FPD-Link III streams to FPD-Link (OpenLDI) interface format. The deserializer can run on 50 Ω single ended coaxial or 100 Ω differential shielded twisted pair (STP) cable with cost efficiency. It can recover data from a single or dual channel FPD-Link III serial stream, and then convert it to a dual pixel FPD-Link (8 LVDS data channels+clock). It can support up to 2K (2048x1080) video resolution (24 bit color depth). This provides a bridge between HDMI capable sources, such as CPUs, to connect to existing LVDS displays or application processors.
FPD-Link III interface supports video and audio data transmission and full duplex control (including I2C and SPI communication) through the same differential link. The integration of video data and control through two differential pairs can reduce the size and weight of the interconnect and simplify the system design. Electromagnetic interference (EMI) is minimized by using low voltage differential signaling, data exchange, and random generation. In backward compatibility mode, the device can support up to WXGA and 720p resolution (24 bit color depth) on a single differential link.
The device will automatically detect FPD-Link III channels and provide a clock alignment and offset compensation function without any special training mode. This ensures that the phase offset is within tolerance when there are mismatches in interconnecting circuits (e.g. PCB wiring), differences in cable pair lengths, and connector imbalance.
characteristic
Meet the requirements of automobile application
The following results comply with AEC Q100 standard:
Device temperature level 2: ambient operating temperature range from - 40 ℃ to+105 ℃
Support pixel clock frequency up to 192 MHz, and achieve resolution up to 2K (2048x1080) (24 bit color depth)
Single or dual channel FPD-Link III interface with offset compensation capability
Single or dual channel OpenLDI (LVDS) transmitter
Single channel: up to 96MHz pixel clock
Dual channel: up to 192MHz pixel clock
Configurable 18 bit RGB or 24 bit RGB
Integrated HDCP cipher engine with on-chip key storage
Support HDCP repeater application
Four channel high-speed GPIO (up to 2Mbps per channel)
Adaptive reception equalization
At 1.7GHz, channel insertion loss compensation is up to – 15.3dB
Provide automatic temperature and cable aging compensation
SPI control interface speed up to 3.3Mbps
I2C with 1Mbps fast mode enhanced version (master/slave)
Image enhancement (white balance and jitter)
Support 7.1 multiple I2S (4 data) channels