Lan9252i / Pt tqfp-64 Ethernet controller chip IC
Lan9252 is a 2 / 3-port Ethernet cat slave controller with dual integrated Ethernet PHY. Each includes a full duplex 100base-tx transceiver and supports 100Mbps (100base-tx) operation. Lan9252 supports hpautomdix and allows the use of direct connection or cross LAN cables. 100Base-FX is supported by an external optical transceiver.
The lan9252 includes a fieldbus memory management unit (FMMU) with 4K byte dual port memory (DPRAM) and three dual port slave controllers. Each FMMU performs the task of mapping logical addresses to physical addresses. The EtherCAT slave controller also includes four synchronization managers to allow data exchange between the EtherCAT master server and the local application. The operating direction and operating mode of each synchronization manager are configured by the EtherCAT host. There are two operation modes: buffer mode or mailbox mode. In buffer mode, both the local microcontroller and EtherCAT master server can write to the device at the same time. The buffer in lan9252 will always contain newer data. If the new data reaches the old data before reading, the old data will be deleted. In mailbox mode, the local microcontroller and EtherCAT master server access the buffer using the handshake to ensure that data will not be deleted.
Two user selectable host bus interface options are available:
Index register access this implementation provides three index / data register libraries, each of which has an independent conversion from byte / word to DWORD. The internal register can * write to one of the three index registers, and then read or write to the corresponding data register. The three index / data register libraries support more than three independent driver threads without access conflicts. Each thread can write to its allocated index register without another thread overwriting it. In the same 32-bit index / data register, two 16 bit cycles or four 8-bit cycles are required -- however, these accesses can be interleaved. Support direct (non indexed) read and write access to process data FIFOs. Direct FIFO access provides independent conversion from byte / word to DWORD, and supports cross access with index / data registers.
Multiple address / data bus this implementation provides multiple address and data buses with single-phase and two-phase address support. Address load address strobe, and then use read or write strobe for data access. In the same 32-bit DWORD, two back-to-back 16 bit data cycles or four back-to-back 8-bit data cycles are required. These accesses must be sequential without any interleaved access to other registers. By executing one address cycle and then multiple read or write data cycles, burst read and write access to process data FIFOs is supported.
HBI supports 8/16 bit operations, including large, small and mixed environment operations. The two processing data ramfifos interface the HBI with the EtherCAT slave controller to facilitate the transmission of processing data information between the host CPU and the EtherCAT slave. A configurable host interrupt pin allows the device to notify the host CPU of any internal interrupt.
SPI / quadspi slave controller provides a synchronous slave interface with low pin count, which facilitates the communication between the equipment and the host system. The SPI / quadspi slave server allows access to the system CSR, internal FIFO and memory. It supports single and multiple register read and write commands and increment, decrease and static addressing. Single, dual and four bit channels support clock rates up to 80MHz.
Lan9252 supports many power management and wake-up functions. Several methods, including "wake-up by LAN" and "wake-up by n9252 *" can be programmed to "wake-up by LAN" and "wake-up by external * signals, and can be changed to" wake-up by LAN ". This signal is an ideal signal to trigger the system power supply using a remote Ethernet wake-up event. The device can be removed from the low power state by a host processor command or one of the wake-up events.
For simple digital modules without microcontroller, lan9252 can also operate in digital input / O mode, in which 16 digital signals can be controlled or monitored by EtherCAT master server.
To enable a star or tree network topology, the device can be configured as a 3-port slave server, providing an additional MII port. This port can be connected to an external PHY, form a faucet along the current daisy chain, or connect to another lan9252 that creates a 4-port solution. MII ports can point upstream (such as port 0) or downstream (as port 2)
LED support includes a standard run indicator and a link / activity indicator for each port. It includes a 64 bit distributed clock to realize * * synchronization and provide accurate information about the local timing of data acquisition.
The lan9252 can be configured to operate with an integrated 3.3V to 1.2V linear regulator from a single 3.3V power supply. The linear regulator can be optionally disabled, allowing the use of external regulators to reduce system power consumption.
Collection
• 2 / 3 port EtherCAT slave controller with 3 fieldbuses
Memory management unit (FMMU) and
4 synchronization managers
• interface with most 8 / 16 bit embedded controllers
And a 32-bit embedded controller with 8 / 16 bits
bus
• Ethernet physical devices integrated with HP auto mdix
• wake on LAN (WOL) support
• low power mode allows the system to go to sleep
Mode until host addressing
• cable diagnostic support
• 1.8V to 3.3V variable voltage I / O
• integrated 1.2V regulator for single 3.3V operation
• low number of pins and small body size
Target application
• motor motion control
• process / plant automation
• communication module, interface card
• sensors
• hydraulic and pneumatic valve systems
• operator interface
Main benefits
• integrated * * 100Mbps Ethernet
transceiver
-IEEE 802.3/802.3u compliant (* * Ethernet)
-Support 100Base-FX through external optical transceiver
-Loopback mode
-Automatic polarity detection and correction
-HP automatic mdix
• EtherCAT slave controller
-Support 3 FMMU
-Supports 4 synchronization managers
-Distributed clock support allows and
Other EtherCAT devices
-4K byte DPRAM
• 8 / 16 bit host bus interface
-Index register or multiplex bus
-Allow the local host to enter sleep mode until
Aether cat master
-SPI / quad SPI support
• digital I / O mode to optimize system cost
• * three ports for flexible network configuration
• comprehensive power management capabilities
-3 power off levels
-Link wake-up state change (energy detection)
-Magic packet wake-up, local area network wake-up (WOL), wake-up
Broadcast, wake up on * *'s Da
-Wake up indicator event signal
• power and I / O
-Integrated power on reset circuit
-Locking performance * over 150mA
According to EIA / jesd78, level II
-JEDEC class 3A ESD performance
-Single 3.3V power supply
(integrated 1.2V regulator)
• additional functions
-Multifunctional gpios
-Be able to use low-cost 25MHz crystal to reduce BOM
• packaging
-Lead free RoHS compatible 64 pin QFN or 64 pin TQFP EP
• available for commercial, industrial and expansion
The lan9252 includes a fieldbus memory management unit (FMMU) with 4K byte dual port memory (DPRAM) and three dual port slave controllers. Each FMMU performs the task of mapping logical addresses to physical addresses. The EtherCAT slave controller also includes four synchronization managers to allow data exchange between the EtherCAT master server and the local application. The operating direction and operating mode of each synchronization manager are configured by the EtherCAT host. There are two operation modes: buffer mode or mailbox mode. In buffer mode, both the local microcontroller and EtherCAT master server can write to the device at the same time. The buffer in lan9252 will always contain newer data. If the new data reaches the old data before reading, the old data will be deleted. In mailbox mode, the local microcontroller and EtherCAT master server access the buffer using the handshake to ensure that data will not be deleted.
Two user selectable host bus interface options are available:
Index register access this implementation provides three index / data register libraries, each of which has an independent conversion from byte / word to DWORD. The internal register can * write to one of the three index registers, and then read or write to the corresponding data register. The three index / data register libraries support more than three independent driver threads without access conflicts. Each thread can write to its allocated index register without another thread overwriting it. In the same 32-bit index / data register, two 16 bit cycles or four 8-bit cycles are required -- however, these accesses can be interleaved. Support direct (non indexed) read and write access to process data FIFOs. Direct FIFO access provides independent conversion from byte / word to DWORD, and supports cross access with index / data registers.
Multiple address / data bus this implementation provides multiple address and data buses with single-phase and two-phase address support. Address load address strobe, and then use read or write strobe for data access. In the same 32-bit DWORD, two back-to-back 16 bit data cycles or four back-to-back 8-bit data cycles are required. These accesses must be sequential without any interleaved access to other registers. By executing one address cycle and then multiple read or write data cycles, burst read and write access to process data FIFOs is supported.
HBI supports 8/16 bit operations, including large, small and mixed environment operations. The two processing data ramfifos interface the HBI with the EtherCAT slave controller to facilitate the transmission of processing data information between the host CPU and the EtherCAT slave. A configurable host interrupt pin allows the device to notify the host CPU of any internal interrupt.
SPI / quadspi slave controller provides a synchronous slave interface with low pin count, which facilitates the communication between the equipment and the host system. The SPI / quadspi slave server allows access to the system CSR, internal FIFO and memory. It supports single and multiple register read and write commands and increment, decrease and static addressing. Single, dual and four bit channels support clock rates up to 80MHz.
Lan9252 supports many power management and wake-up functions. Several methods, including "wake-up by LAN" and "wake-up by n9252 *" can be programmed to "wake-up by LAN" and "wake-up by external * signals, and can be changed to" wake-up by LAN ". This signal is an ideal signal to trigger the system power supply using a remote Ethernet wake-up event. The device can be removed from the low power state by a host processor command or one of the wake-up events.
For simple digital modules without microcontroller, lan9252 can also operate in digital input / O mode, in which 16 digital signals can be controlled or monitored by EtherCAT master server.
To enable a star or tree network topology, the device can be configured as a 3-port slave server, providing an additional MII port. This port can be connected to an external PHY, form a faucet along the current daisy chain, or connect to another lan9252 that creates a 4-port solution. MII ports can point upstream (such as port 0) or downstream (as port 2)
LED support includes a standard run indicator and a link / activity indicator for each port. It includes a 64 bit distributed clock to realize * * synchronization and provide accurate information about the local timing of data acquisition.
The lan9252 can be configured to operate with an integrated 3.3V to 1.2V linear regulator from a single 3.3V power supply. The linear regulator can be optionally disabled, allowing the use of external regulators to reduce system power consumption.
Collection
• 2 / 3 port EtherCAT slave controller with 3 fieldbuses
Memory management unit (FMMU) and
4 synchronization managers
• interface with most 8 / 16 bit embedded controllers
And a 32-bit embedded controller with 8 / 16 bits
bus
• Ethernet physical devices integrated with HP auto mdix
• wake on LAN (WOL) support
• low power mode allows the system to go to sleep
Mode until host addressing
• cable diagnostic support
• 1.8V to 3.3V variable voltage I / O
• integrated 1.2V regulator for single 3.3V operation
• low number of pins and small body size
Target application
• motor motion control
• process / plant automation
• communication module, interface card
• sensors
• hydraulic and pneumatic valve systems
• operator interface
Main benefits
• integrated * * 100Mbps Ethernet
transceiver
-IEEE 802.3/802.3u compliant (* * Ethernet)
-Support 100Base-FX through external optical transceiver
-Loopback mode
-Automatic polarity detection and correction
-HP automatic mdix
• EtherCAT slave controller
-Support 3 FMMU
-Supports 4 synchronization managers
-Distributed clock support allows and
Other EtherCAT devices
-4K byte DPRAM
• 8 / 16 bit host bus interface
-Index register or multiplex bus
-Allow the local host to enter sleep mode until
Aether cat master
-SPI / quad SPI support
• digital I / O mode to optimize system cost
• * three ports for flexible network configuration
• comprehensive power management capabilities
-3 power off levels
-Link wake-up state change (energy detection)
-Magic packet wake-up, local area network wake-up (WOL), wake-up
Broadcast, wake up on * *'s Da
-Wake up indicator event signal
• power and I / O
-Integrated power on reset circuit
-Locking performance * over 150mA
According to EIA / jesd78, level II
-JEDEC class 3A ESD performance
-Single 3.3V power supply
(integrated 1.2V regulator)
• additional functions
-Multifunctional gpios
-Be able to use low-cost 25MHz crystal to reduce BOM
• packaging
-Lead free RoHS compatible 64 pin QFN or 64 pin TQFP EP
• available for commercial, industrial and expansion
Industrial * temperature. Range
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