General Description
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory contain
ing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchro
nous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4
bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by
8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns
by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se
quence. Accesses begin with the registration of an ACTIVE command, which is then fol
lowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank; A[12:0] select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high
speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran
dom-access operation.
The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and out
puts are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications:
• 16ms refresh rate
• Self refresh not supported
• Ambient and case temperature cannot be less than –40°C or greater than +105°C
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 8192-cycle refresh (commercial and
industrial)
– 16ms, 8192-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Options Marking
• Configurations
– 64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4
– 32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8
– 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16
• Write recovery (t
WR)
– t
WR = 2 CLK A2
• Plastic package – OCPL1
– 54-pin TSOP II OCPL1 (400 mil)
(standard)
TG
– 54-pin TSOP II OCPL1 (400 mil)
Pb-free
P
Options Marking
– 60-ball TFBGA (x4, x8) (8mm x
16mm)
FB
– 60-ball TFBGA (x4, x8) (8mm x
16mm) Pb-free
BB
– 54-ball VFBGA (x16) (8mm x 14 mm) FG2
– 54-ball VFBGA (x16) (8mm x 14 mm)
Pb-free
BG2
– 54-ball VFBGA (x16) (8mm x 8 mm) F43
– 54-ball VFBGA (x16) (8mm x 8 mm)
Pb-free
B43
• Timing – cycle time
– 6ns @ CL = 3 (x8, x16 only) -6A
– 7.5ns @ CL = 3 (PC133) -752
– 7.5ns @ CL = 2 (PC133) -7E
• Self refresh
– Standard None
– Low power L2, 4
• Operating temperature range
– Commercial (0˚C to +70˚C) None
– Industrial (–40˚C to +85˚C) IT
– Automotive (–40˚C to +105˚C) AT4
• Revision :D/:G
Notes: 1. Off-center parting line.
2. Only available on Revision D.
3. Only available on Revision G.
4. Contact Micron for availability.
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