Mt41k256m16tw-107ait: P fbga-96 8x14 storage in stock

Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data

rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words

per clock cycle atthe I/O pins. Asingle read orwrite operation forthe DDR3 SDRAM effectively consists

of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corre-

sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data

capture at the DDR3 SDRAM inputreceiver. DQS is center-aligned with data for WRITEs. The read data

is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes.

The DDR3 SDRAM operates from a differential clock (CKandCK#). The crossing ofCKgoingHIGH and

CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are

registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the

WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ

preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location

and continue for a programmed number of locations in a programmed sequence. Accesses begin with

the registration of an ACTIVATE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVATE command are used to select the bank and

row to be accessed. The address bits registered coincident with the READ or WRITE commands are

used to select the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to

provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for

concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed

–40°C or 95°C. JEDEC specifications require the refresh rate to double when TCexceeds 85°C; this also

requires use of the high-temperature self refresh option. Additionally, ODT resistance and the

input/output impedance must be derated when TCis < 0°C or >85°C.

Automotive Temperature

The automotive temperature (AT) device requires that the case temperature not exceed

–40°C or 105°C. JEDEC specifications require the refresh rate to double when TCexceeds 85°C; this also

requires use of the high-temperature self refresh option. Additionally, ODT resistance and the

input/output impedance must be derated when TCis < 0°C or >85°C.

Ultra-high Temperature

The Ultra-high temperature (UT) device requires that the case temperature not exceed

–40°C or 125°C. JEDEC specifications require the refresh rate to double when TCexceeds 85°C; this also

requires use of the high-temperature auto refresh option. When Tc > +105C, the refresh rate must be

increased to 8X. Self-refresh mode is not available for Tc >+105°C. Additionally,ODTresistance andthe

input/output impedance must be derated when TCis < 0°C or >85°C.

DDR3L SDRAM (1.35V) is a low voltage version of the

DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM (Die

Rev :E) data sheet specifications when running in 1.5V

compatible mode.

Features

• VDD = VDDQ = 1.35V (1.283–1.45V)

• Backward compatible to VDD = VDDQ = 1.5V ±0.075V

– Supports DDR3L devices to be backward compati

ble in 1.5V applications

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• TC of -40°C to +125°C

– 64ms, 8192-cycle refresh at -40°C to +85°C

– 32ms at +85°C to +105°C

– 16ms at +105°C to +115°C

– 8ms at +115°C to +125°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multipurpose register

• Output driver calibration

• AEC-Q100

Options

Marking

• Configuration

– 512 Meg x 8

512M8

– 256 Meg x 16

256M16

• FBGA package (Pb-free) –

– 78-ball (8mm x

10.5mm)

• FBGA package (Pb-free) –

x16

– 96-ball (8mm x 14mm)

• Timing – cycle time

– 1.07ns @ CL = 13

(DDR3-1866)

-107

• Automotive grade

– AEC-Q100

– PPAP submission

• Operating temperature

– Industrial (–40°C ≤ TC ≤

+95°C)

– Automotive (–40°C ≤ TC

≤ +105°C)

– Ultra-high (–40°C ≤ TC ≤

+125°C)3

• Revision