Tms320lf2406apza digital signal processor and controller
Tms320lf240xa and tms320lc240xa devices, new members of the TMS320C24x generation digital signal processor (DSP) controller, are part of the tms320c2000 platform of fixed-point DSP. The 240xa device provides the enhanced TMS320 DSP architecture design of c2xx core CPU for low-cost, low-power and high-performance processing capacity. Several advanced peripherals, optimized digital motor and motion control applications, have been integrated to provide a real MCU DSP controller. Although the code is compatible with the existing c24x DSP controller equipment, 240xa provides higher processing performance (40mips) and higher level of peripheral integration.
The 240xa generation provides a range of memory sizes and different peripherals to meet the specific price / performance points required by various applications. Flash memory devices up to 32K words provide a cost-effective reprogrammable solution for capacity production. 240xa device provides password based "code security" function, which can prevent illegal duplication of proprietary code stored in on-chip flash memory / ROM. Note that the flash based device contains a 256 word boot ROM to facilitate in circuit programming. The 240xa series also includes ROM devices that are fully compatible with ROM devices.
All 240xa devices provide at least one event manager module, which has been optimized for digital motor control and power conversion applications. The functions of the module include center and / or edge aligned PWM generation, programmable dead band to prevent penetration failure, and synchronous analog-to-digital conversion. Devices with dual event managers can enable multiple motor and / or converter control using a single 240xadp controller. Selecting the EV pin has provided an "input qualifier" circuit to reduce accidental pin triggering.
The high-performance 10 bit analog-to-digital converter (ADC) has a minimum conversion time of 375ns and provides up to 16 channels of analog input. The automatic sorting function of ADC allows up to 16 conversions in a single conversion session without any CPU overhead.
A serial communication interface (SCI) is integrated on all devices to provide asynchronous communication for other devices in the system. For systems requiring additional communication interfaces, 2407a, 2406a, 2404a and 2403a provide a 16 bit synchronous serial peripheral interface (SPI). 2407a, 2406a and 2403a provide controller area network (can) communication modules that meet the 2.0B specification. In order to maximize the flexibility of the device, the function pin can also be configured as general input / output (GPIO).
In order to simplify the development time, JTAG compatible scan based simulation has been integrated into all devices. This provides the non-invasive real-time function required to debug the digital control system. A complete set of code generation tools from C compiler to industry standard coder studio debugger support this series. Many third-party developers not only provide equipment level development tools, but also provide system level design and development support.
High performance static CMOS technology
− 25 ns command cycle time (40 MHz)
− 40 MIPS performance
− low power 3.3-V design
DSP CPU core based on TMS320C2xx
− code compatible with F243 / f241 / c242
− instruction set and module compatibility
Use F240
Flash (LF) and ROM (LC) device options
− LF240xA:LF2407A，LF2406A，
LF2403A、LF2402A
− LC240xA:LC2406A、LC2404A、，
LC2403A、LC2402A
On chip memory
− up to 32K words x 16 bit flash memory
EEPROM (4 sectors) or ROM
− programmable "code safety" function
For on-chip flash / ROM
− up to 2.5k words x 16 digits
Data / program RAM
− ram 544 dual word access
− single access ram up to 2K words
Boot ROM (lf240xa device)
− SCI / SPI boot loader
Up to two event manager (EV) modules
(EVA and EVB), each including:
− two 16 Bit Universal timers
− eight channel 16 bit pulse width modulation
(PWM) channels that enable the following functions:
− three phase inverter control
− center or edge alignment of PWM
channel
− emergency PWM channel off
With external pdpintx pin
− programmable dead time (dead time)
Prevent penetration failure
− three capture units for timestamp
External event analysis
− select the input qualifier of the pin
− on chip position encoder interface
Circuit
− synchronous A-D conversion
− designed for AC induction, brushless DC,
Switched reluctance motor and stepper motor
control
− for multiple motors and / or
Frequency converter control
External memory interface (LF2407A)
− 192K words x 16 bits total memory:
64K program, 64K data, 64K I / O
Watchdog timer (WD) module
10 bit analog-to-digital converter (ADC)
− 8 or 16 multiplexed input channels
− 500 nanosecond conversion time
− optional dual 8-state sequencer
Triggered by two event managers
Controller area network (can) 2.0B module
（LF2407A、2406A、2403A）
Serial communication interface (SCI)
16 bit serial peripheral interface (SPI)
（LF2407A、2406A、LC2404A、2403A）
Clock based on phase locked loop (PLL)
Generation
Up to 40 individually programmable,
Multiple universal I / O
(GPIO) pin
Up to five external interrupts (power driven)
Protection, reset, two maskable interrupts)
Power management:
− three power-off modes
− be able to turn off the power of each peripheral device
Independently
Real time compatible scanning based on JTAG
Simulation, IEEE standard 1149.1 † (JTAG)
Development tools include:
− Texas Instruments (TI) ANSI C compiler,
Assembler / linker and code generator
Studio debugger
− evaluation module
− scan based self simulation (xds510 ) − extensive third-party digital motor control
support
Package options
− 144 pin LQFP PGE (LF2407A)
− 100 pin LQFP PZ (2406a, lc2404a)
− 64 pin TQFP PAG (lf2403a, lc2403a,
Legislative Council resolution 2402a)
− 64 pin QFP PG (2402a)
Extended temperature options (A and s)
− A: − 40 ° C to 85 ° C − s: − 40 ° C to 125 ° C
The 240xa generation provides a range of memory sizes and different peripherals to meet the specific price / performance points required by various applications. Flash memory devices up to 32K words provide a cost-effective reprogrammable solution for capacity production. 240xa device provides password based "code security" function, which can prevent illegal duplication of proprietary code stored in on-chip flash memory / ROM. Note that the flash based device contains a 256 word boot ROM to facilitate in circuit programming. The 240xa series also includes ROM devices that are fully compatible with ROM devices.
All 240xa devices provide at least one event manager module, which has been optimized for digital motor control and power conversion applications. The functions of the module include center and / or edge aligned PWM generation, programmable dead band to prevent penetration failure, and synchronous analog-to-digital conversion. Devices with dual event managers can enable multiple motor and / or converter control using a single 240xadp controller. Selecting the EV pin has provided an "input qualifier" circuit to reduce accidental pin triggering.
The high-performance 10 bit analog-to-digital converter (ADC) has a minimum conversion time of 375ns and provides up to 16 channels of analog input. The automatic sorting function of ADC allows up to 16 conversions in a single conversion session without any CPU overhead.
A serial communication interface (SCI) is integrated on all devices to provide asynchronous communication for other devices in the system. For systems requiring additional communication interfaces, 2407a, 2406a, 2404a and 2403a provide a 16 bit synchronous serial peripheral interface (SPI). 2407a, 2406a and 2403a provide controller area network (can) communication modules that meet the 2.0B specification. In order to maximize the flexibility of the device, the function pin can also be configured as general input / output (GPIO).
In order to simplify the development time, JTAG compatible scan based simulation has been integrated into all devices. This provides the non-invasive real-time function required to debug the digital control system. A complete set of code generation tools from C compiler to industry standard coder studio debugger support this series. Many third-party developers not only provide equipment level development tools, but also provide system level design and development support.
High performance static CMOS technology
− 25 ns command cycle time (40 MHz)
− 40 MIPS performance
− low power 3.3-V design
DSP CPU core based on TMS320C2xx
− code compatible with F243 / f241 / c242
− instruction set and module compatibility
Use F240
Flash (LF) and ROM (LC) device options
− LF240xA:LF2407A，LF2406A，
LF2403A、LF2402A
− LC240xA:LC2406A、LC2404A、，
LC2403A、LC2402A
On chip memory
− up to 32K words x 16 bit flash memory
EEPROM (4 sectors) or ROM
− programmable "code safety" function
For on-chip flash / ROM
− up to 2.5k words x 16 digits
Data / program RAM
− ram 544 dual word access
− single access ram up to 2K words
Boot ROM (lf240xa device)
− SCI / SPI boot loader
Up to two event manager (EV) modules
(EVA and EVB), each including:
− two 16 Bit Universal timers
− eight channel 16 bit pulse width modulation
(PWM) channels that enable the following functions:
− three phase inverter control
− center or edge alignment of PWM
channel
− emergency PWM channel off
With external pdpintx pin
− programmable dead time (dead time)
Prevent penetration failure
− three capture units for timestamp
External event analysis
− select the input qualifier of the pin
− on chip position encoder interface
Circuit
− synchronous A-D conversion
− designed for AC induction, brushless DC,
Switched reluctance motor and stepper motor
control
− for multiple motors and / or
Frequency converter control
External memory interface (LF2407A)
− 192K words x 16 bits total memory:
64K program, 64K data, 64K I / O
Watchdog timer (WD) module
10 bit analog-to-digital converter (ADC)
− 8 or 16 multiplexed input channels
− 500 nanosecond conversion time
− optional dual 8-state sequencer
Triggered by two event managers
Controller area network (can) 2.0B module
（LF2407A、2406A、2403A）
Serial communication interface (SCI)
16 bit serial peripheral interface (SPI)
（LF2407A、2406A、LC2404A、2403A）
Clock based on phase locked loop (PLL)
Generation
Up to 40 individually programmable,
Multiple universal I / O
(GPIO) pin
Up to five external interrupts (power driven)
Protection, reset, two maskable interrupts)
Power management:
− three power-off modes
− be able to turn off the power of each peripheral device
Independently
Real time compatible scanning based on JTAG
Simulation, IEEE standard 1149.1 † (JTAG)
Development tools include:
− Texas Instruments (TI) ANSI C compiler,
Assembler / linker and code generator
Studio debugger
− evaluation module
− scan based self simulation (xds510 ) − extensive third-party digital motor control
support
Package options
− 144 pin LQFP PGE (LF2407A)
− 100 pin LQFP PZ (2406a, lc2404a)
− 64 pin TQFP PAG (lf2403a, lc2403a,
Legislative Council resolution 2402a)
− 64 pin QFP PG (2402a)
Extended temperature options (A and s)
− A: − 40 ° C to 85 ° C − s: − 40 ° C to 125 ° C