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General Description

Micron NAND Flash devices include an asynchronous data interface for high-perform

ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer

commands, address, and data. There are five control signals used to implement the asyn

chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control

hardware write protection and monitor device status (R/B#).

This hardware interface creates a low pin-count device with a standard pinout that re

mains the same from one density to another, enabling future upgrades to higher densi

ties with no board redesign.

A target is the unit of memory accessed by a chip enable signal. A target contains one or

more NAND Flash die. A NAND Flash die is the minimum unit that can independently

execute commands and report status. A NAND Flash die, in the ONFI specification, is

referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable

signal. For further details, see Device and Array Organization.

Features
• Open NAND Flash Interface (ONFI) 1.0-compliant1 • Single-level cell (SLC) technology
• Organization
– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Device size: 1Gb: 1024 blocks
• Asynchronous I/O performance
– tRC/tWC: 20ns (3.3V), 25ns (1.8V)
• Array performance
– Read page: 25µs3 – Program page: 200µs (TYP, 3.3V and 1.8V)3 – Erase block: 700µs (TYP)
• Command set: ONFI NAND Flash Protocol
• Advanced command set
– Program page cache mode5 – Read page cache mode5 – One-time programmable (OTP) mode
– Read unique ID
– Internal data move
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Internal data move operations supported within the
device from which data is read
• Ready/busy# (R/B#) signal provides a hardware
method for detecting operation completion
• WP# signal: write protect entire device
• First block (block address 00h) is valid when shipped from factory with ECC. For minimum required
ECC, see Error Management.
• Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000
• RESET (FFh) required as first command after poweron
• Alternate method of device initialization (Nand_Init) after power up4
(contact factory)
• Quality and reliability
– Data retention: 10 years
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCC: 1.7–1.95V
• Operating temperature:
– Commercial: 0°C to +70°C
– Extended (ET): –40ºC to +85ºC
• Package
– 48-pin TSOP type 1, CPL2 – 63-ball VFBGA