General Description
Serial peripheral interface (SPI) NAND is an SLC NAND Flash memory device that pro
vides a cost-effective nonvolatile memory storage solution where pin count must be
kept to a minimum. It is also an alternative solution to SPI NOR, offering superior write
performance and cost per bit over SPI NOR. The hardware interface creates a low pin
count device with a standard pinout that remains the same from one density to another
and supports future upgrades to higher densities without board redesign.
The serial electrical interface follows the industry-standard serial peripheral interface.
New command protocols and registers are defined for SPI operation. The command set
resembles common SPI-NOR command sets, modified to handle NAND specific func
tions and additional new features.
New features include user-selectable internal ECC and first page auto-load on power
up. SPI NAND Flash devices have six signal lines plus VCC and ground (GND). The sig
nal lines are SCK (serial clock), SI, SO (for command/response and data input/output),
and control signals CS, HOLD#, WP#. This hardware interface creates a low pin-count
device with a standard pinout that remains the same from one density to another, sup
porting future upgrades to higher densities without board redesign.
Each block of the serial NAND Flash device is divided into 64 programmable pages,
each page consisting of 2176 bytes. Each page is further divided into a 2048-byte data
storage region and a 128-byte spare area. The 128-byte area is typically used for memory
and error management functions.
With internal ECC enabled as the default after power on, ECC code is generated inter
nally when a page is written to the memory core. The ECC code is stored in the spare
area of each page. When a page is read to the cache register, the ECC code is calculated
again and compared with the stored value. Errors are corrected if necessary. The device
either outputs corrected data or returns an ECC error status. The internal ECC can be
configured off after device initialization. Contact Micron representative if ECC is re
quired to be default off after power on.
The first eight blocks are valid when shipped from factory. Security functions are also
provided including software block protection: Lock tight and hardware protection
modes avoid array data corruption.
Features
• Single-level cell (SLC) technology
• 2Gb density
• Organization
– Page size x1: 2176 bytes (2048 + 128 bytes)
– Block size: 64 pages (128K + 8K bytes)
– Plane size: 2Gb (2 planes, 1024 blocks per plane)
• Standard and extended SPI-compatible serial bus
interface
– Instruction, address on 1 pin; data out on 1, 2, or
4 pins
– Instruction on 1 pin; address, data out on 2 or 4
pins
– Instruction, address on 1 pin; data in on 1 or 4
pins
• User-selectable internal ECC supported
– 8 bits/sector
• Array performance
– 133 MHz clock frequency (MAX)
– Page read: 25µs (MAX) with on-die ECC disabled;
70µs (MAX) with on-die ECC enabled
– Page program: 200µs (TYP) with on-die ECC disabled; 220µs (TYP) with on-die ECC enabled
– Block erase: 2ms (TYP)
• Advanced features
– Read page cache mode
– Read unique ID
– Read parameter page
• Device initialization
– Automatic device initialization after power-up
• Security
– Blocks 7:0 are valid when shipped from factory
with ECC enabled
– Software write protection with lock register
– Hardware write protection to freeze BP bits
– Lock tight to freeze BP bits during one power cycle
• Permanent block lock protection
– OTP Space: 10 pages one-time programmable
NAND Flash memory area
• Operating voltage range
– VCC = 2.7–3.6V
• Operating temperature
– Industrial: –40°C to +85°C
• Quality and reliability
– Endurance: 100,000 PROGRAM/ERASE cycles
– Data retention: JESD47H-compliant; see qualification report
– Additional: Uncycled data retention: 10 years
24/7 @85°C
• Package
– 16-pin SOP, 300 mils (package code: SF)
– 8-pin U-PDFN, 8mm x 6mm x 0.65mm (MLP8)
(package code: WB)
– 24-ball T-PBGA, 05/6mm x 8mm (5 x 5 array)
(package code: 12)
