Mt41k128m16jt-125: K magnesium optical memory

The 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM device. Unless stated otherwise, the DDR3L SDRAM device meets the functional and timing specifications listed in the equivalent density standard or automotive DDR3 SDRAM data sheet located on www.micron.com.

Features
• VDD = VDDQ = 1.35V (1.283–1.45V)
• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options Marking
• Configuration
– 512 Meg x 4 512M4
– 256 Meg x 8 256M8
– 128 Meg x 16 128M16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm)
Rev. H, M, K
DA
– 78-ball FBGA (9mm x 11.5mm)
Rev. D
HX
• FBGA package (Pb-free) – x16
– 96-ball FBGA (9mm x 14mm)
Rev. D
HA
– 96-ball FBGA (8mm x 14mm)
Rev. K
JT
• Timing – cycle time
– 1.071ns @ CL = 13 (DDR3-1866) -107
– 1.25ns @ CL = 11 (DDR3-1600) -125
– 1.5ns @ CL = 9 (DDR3-1333) -15E
– 1.875ns @ CL = 7 (DDR3-1066) -187E
• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C) None
– Industrial (–40°C ≤ TC ≤ +95°C) IT
• Revision :D/ :H/ :K/ :M