Mt46h64m32lfbq-48 AIT: original agent of C magnesium optical access memory

General Description

The 2Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-ac

cess memory containing 2,147,483,648 bits. It is internally configured as a quad-bank

DRAM. Each of the x16’s 536,870,912-bit banks is organized as 16,384 rows by 2048 col-

umns by 16 bits. Each of the x32’s 536,870,912-bit banks is organized as 16,384 rows by

1024 columns by 32 bits.

Features
• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)2
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh; 32ms for the automotive temperature
range
Options Mark
• VDD/VDDQ
– 1.8V/1.8V H
• Configuration
– 128 Meg x 16 (32 Meg x 16 x 4 banks) 128M16
– 64 Meg x 32 (16 Meg x 32 x 4 banks) 64M32
• Addressing
– JEDEC-standard LF
• Plastic "green" package
– 60-ball VFBGA (8mm x 9mm) DD
– 90-ball VFBGA (8mm x 13mm) BQ
• Timing – cycle time
– 4.8ns @ CL = 3 (208 MHz) -48
• Special Options
– Automotive (package-level burn-in) A
• Operating temperature range
– From –40˚C to +85˚C IT
– From –40˚C to +105˚C1 AT
• Design revision :C