8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns
by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se
quence. Accesses begin with the registration of an ACTIVE command, which is then fol
lowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank; A[11:0] select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high
speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran
dom-access operation.
The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and out
puts are LVTTL-compatible.
The devices offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
Automotive Temperature
The automotive temperature (AAT) option adheres to the following specifications:
• 16ms auto refresh rate required above 85°C
• Self refresh not supported above 85°C
• Ambient and case temperature cannot be less than –40°C or greater than +105°C
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full
page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Auto refresh mode; standard and low power
– 64ms, 4096-cycle (industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• AEC-Q100
• PPAP submission
• 8D response time
Options Marking
• Configurations
– 32 Meg x 4 (8 Meg x 4 x 4 banks)1 32M4
– 16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8
– 8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16
• Write recovery (tWR)
Options Marking
– tWR = 2 CLK A2
• Plastic package – OCPL2
– 54-pin TSOP II (400 mil) TG
– 54-pin TSOP II (400 mil) Pb-free P
– 60-ball FBGA (8mm x 16mm) FB1
– 60-ball FBGA (8mm x 16mm) Pb-free BB1
– 54-ball VFBGA (x16 only) (8mm x
8mm)
F4
– 54-ball VFBGA (x16 only) (8mm x
8mm) Pb-free
B4
• Timing – cycle time
– 7.5ns @ CL = 3 (PC133) -753
– 7.5ns @ CL = 2 (PC133) -7E
– 6.0ns @ CL = 3 (x16 only) -6A
• Self refresh
– Standard None
– Low power L3
• Revision :G/:L
• Operating temperature range
– Industrial (–40˚C to +85˚C) AIT
– Automotive (–40˚C to +105˚C) AAT1
