Spc5644af0mlu1r lqfp-176 32-bit microcontroller

Description

This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive

transmission control applications.

It is compatible with devices in Freescale’s MPC5600 family and offers performance and capabilities beyond the MPC5632M

devices.

The microcontroller’s e200z4 host processor core is built on the Power Architecture® technology and designed specifically for

embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal

processing (DSP).

The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM

and a 2 MB internal flash memory.

For development, the device includes a calibration bus that is accessible only when using the Freescale VertiCal Calibration

System.

1.5 Feature details

1.5.1 e200z4 core

MPC5642A devices have a high performance e200z4 core processor:

• 32-bit Power Architecture technology programmer’s model

• Variable Length Encoding (VLE) enhancements

• Dual issue, 32-bit Power Architecture technology compliant CPU

• 8 KB, 2/4-way set associative instruction cache

• Thirty-two 64-bit general purpose registers (GPRs)

• Memory Management Unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)

• Harvard Architecture: Separate instruction bus and load/store bus

• Vectored interrupt support

• Non-maskable interrupt input

• Critical Interrupt input

• New ‘Wait for Interrupt’ instruction, to be used with new low power modes

• Reservation instructions for implementing read-modify-write accesses

• Signal processing extension (SPE) APU

• Single Precision Floating point (scalar and vector)

• Nexus Class 3+ debug

• Process ID manipulation for the MMU using an external tool

• In-order execution and retirement

• Precise exception handling

• Branch processing unit

— Dedicated branch address calculation adder

— Branch target prefetching using 8-entry BTB

• Supports independent instruction and data accesses to different memory subsystems, such as SRAM and flash memory

via independent Instruction and Data BIUs

• Load/store unit

— 2-cycle load latency

— Fully pipelined

— Big and Little endian support

— Misaligned access support

• Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose

• Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations,

using the 64-bit General Purpose Register file

• Power management

— Low power design – extensive clock gating

— Power saving modes: wait

— Dynamic power management of execution units, cache and MMU

• Testability

— Synthesizeable, MuxD scan design

— ABIST/MBIST for arrays

— Built-in Parallel Signature Unit