Mt40a512m16ly-075: e fbga-96 memory MgO sold at a low price
Features
• VDD = VDDQ = 1.2V ±60mV
• VPP = 2.5V, –125mV, +250mV
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• Refresh time of 8192-cycle at TC temperature range:
– 64ms at -40°C to 85°C
– 32ms at >85°C to 95°C
– 16ms at >95°C to 105°C
• 16 internal banks (x4, x8): 4 groups of 4 banks each
• 8 internal banks (x16): 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write leveling
• Self refresh mode
• Low-power auto self refresh (LPASR)
• Temperature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination
(ODT)
• Data bus inversion (DBI) for data bus
• Command/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivity test
• JEDEC JESD-79-4 compliant
• sPPR and hPPR capability
Options1
Marking
• Configuration
– 2 Gig x 4 2G4
– 1 Gig x 8 1G8
– 512 Meg x 16 512M16
• 78-ball FBGA package (Pb-free) – x4,
x8
– 9mm x 13.2mm – Rev. A PM
– 8mm x 12mm – Rev. B, D, G WE
– 7.5mm x 11mm – Rev. E, H, J SA
• 96-ball FBGA package (Pb-free) – x16
– 9mm x 14mm – Rev. A HA
– 8mm x 14mm – Rev. B JY
– 7.5mm x 13.5mm – Rev. D, E, H LY
– 7.5mm x 13mm – Rev. J TB
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200) -062E
– 0.682ns @ CL = 21 (DDR4-2933) -068
– 0.750ns @ CL = 19 (DDR4-2666) -075
– 0.750ns @ CL = 18 (DDR4-2666) -075E
– 0.833ns @ CL = 17 (DDR4-2400) -083
– 0.833ns @ CL = 16 (DDR4-2400) -083E
– 0.937ns @ CL = 15 (DDR4-2133) -093E
– 1.071ns @ CL = 13 (DDR4-1866) -107E
• Operating temperature
– Commercial (0° ื TCื 95°C) None
– Industrial (–40° ื TCื 95°C) IT
– Automotive (–40° ื TCื 105°C) AT
• Revision :A, :B, :D, :E,
:G, :H, :J