Mt40a1g16kd-062e DDR SDRAM MgO fbga-96 agent spot
Features
• VDD = VDDQ = 1.2V ±60mV
• VPP = 2.5V, –125mV, +250mV
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• TC maximum up to 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
• 16 internal banks (x4, x8): 4 groups of 4 banks each
• 8 internal banks (x16): 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write leveling
• Self refresh mode
• Low-power auto self refresh (LPASR)
• Temperature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination
(ODT)
• Data bus inversion (DBI) for data bus
• Command/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivity test
• JEDEC JESD-79-4 compliant
• sPPR and hPPR capability
Options1
Marking
• Configuration
– 4 Gig x 4 4G4
– 2 Gig x 8 2G8
– 1 Gig x 16 1G16
• 78-ball FBGA package (Pb-free) – x4, x8
– 10mm x 11mm – Rev. B VA
– 9mm x 11mm – Rev. E JC
• 96-ball FBGA package (Pb-free) – x16
– 10mm x 13mm – Rev. B RC
– 9mm x 13mm – Rev. E KD
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200) -062E
– 0.682ns @ CL = 21 (DDR4-2933) -068
• Operating temperature
– Commercial (0° ื TCื 95°C) None
– Industrial (–40° ื TCื 95°C) IT
• Revision :B, :E