Mt29f32g08cbadbwprdtr tsop-48 memory optical agent

General Description

Micron NAND Flash devices include an asynchronous data interface for high-perform

ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer

commands, address, and data. There are five control signals used to implement the

asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control

hardware write protection (WP#) and monitor device status (R/B#).

This Micron NAND Flash device additionally includes a synchronous data interface for

high-performance I/O operations. When the synchronous interface is active, WE# be

comes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe

(DQS).

This hardware interface creates a low pin-count device with a standard pinout that re

mains the same from one density to another, enabling future upgrades to higher densi

ties with no board redesign.

A target is the unit of memory accessed by a chip enable signal. A target contains one or

more NAND Flash die. A NAND Flash die is the minimum unit that can independently

execute commands and report status. A NAND Flash die, in the ONFI specification, is

referred to as a logical unit (LUN). For further details, see Device and Array Organiza

tion.

Features
• Open NAND Flash Interface (ONFI) 2.3-compliant1
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 8936 bytes (8192 + 744 bytes)
– Block size: 256 pages (2048K + 186K bytes)
– Plane size: 2 planes x 1064 blocks per plane
– Device size: 32Gb: 2128 blocks;
64Gb: 4156 blocks;
• Synchronous I/O performance
– Up to synchronous timing mode 4
– Clock rate: 12ns (DDR)
– Read/write throughput per pin: 166MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
– tRC/tWC: 20ns (MIN)
– Read/write throughput per pin: 50MT/s
• Array performance
– Read page: 100µs (MAX)
– Program page: 1300µs (TYP)
– Erase block: 3ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
– Read Retry
– Single-level cell (SLC) mode2
– User de-selectable data randomization2
• First block (block address 00h) is valid when shipped from factory. For minimum required ECC, see
Error Management (page 108).3
• RESET (FFh) required as first command after power-on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware method for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability3
– Data retention: JESD47 compliant; see qualification report
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
• Package
– 48-pin TSOP