Supply s25fl127sabmfi101 soic-8 nor flash cypress in stock
explain
Cypress s25fl127s device is a flash non-volatile memory product, which uses:
• mirrorbit technology - two data bits are stored in each storage array transistor
• eclipse Architecture - significantly improve program and erase performance
• 65nm process lithography
This device is connected to the host system through serial peripheral interface (SPI). Support traditional SPI unit serial input and output (single I / O or SiO) and optional two bit (dual I / O or DIO) and four bit (quadi / O or QIO) serial commands. This multi wide interface is called SPI / O or Mio.
The eclipse architecture has a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in more efficient programming and erasure than previous generation SPI programs or erasure algorithms.
Executing code directly from flash memory is often referred to as in place execution or XIP. By using the FL-S device at a higher clock rate and using the QIO command, the instruction read transmission rate can match or * pass the traditional parallel interface, asynchronous or flash memory, while significantly reducing the signal count.
S25fl127s products provide high-density products, as well as the flexibility and * * performance required by various embedded applications. It is ideal for code shadowing, XIP, and data storage.
features
• CMOS 3.0V core
• density
– 128 megabytes (16 megabytes)
• serial peripheral interface (SPI) with multiple i/o
– SPI clock polarity and phase modes 0 and 3
– extended addressing: 24 bit or 32-bit address options
– serial command sets and footprints are compatible with
S25FL-A，
S25fl-k and s25fl-p SPI series
– multiple I / O command sets and footprints are compatible with
S25fl-p SPI series
read command
– normal, * *, two-way, four-way
– auto start - power up or reset and perform normal or
Automatic quaternion read command at preselected position
address
– CFI data information for configuration.
• programming (0.8 Mbytes / s)
– 256 byte or 512 byte page programming buffer option
– four input page programming (QPP) for slow clock
system
– automatic ECC internal hardware error correction code single bit error correction generation
• erase (0.5 Mbytes / s)
– mixed sector size option - sixteen 4-kbyte physical set address space * or bottom sectors, including all remaining 64 kb sectors
– unified sector option - always erase 256 KB blocks
Software compatibility with * high density and future
Equipment.
• bicycle endurance
– at least 100000 program erase cycles per sector
• data retention
– data retention period of at least 20 years
• safety features
– 1024 byte one time program (OTP) array
– block protection:
– status register bits, used to control the protection against faults
Programming or erasing of continuous sector ranges.
– hardware and software control options
– * * sector protection (ASP)
– single sector protection by boot code or
password
cypress using eclipse's 65 nm mirror bit technology architecture
• power supply voltage: 2.7V to 3.6V
temperature range:
– Industrial (- 40 ° C to + 85 ° C)
– industrial temperature rise (- 40 ° C to + 105 ° C)
– automotive aec-q100 class 3 (- 40 ° C to + 85 ° C)
– automotive aec-q100 class 2 (- 40 ° C to + 105 ° C)
• packaging (all lead-free)
– 8-core SOIC (208 mils)
– 16 core SOIC (300 mils)
– 8-contact sensor on 6 x 5 mm
– bga-24 6 x 8 mm
– floor area of 5 x 5 balls (fab024) and 4 x 6 balls (fac024)
Option
– known good molds and known test molds
Cypress s25fl127s device is a flash non-volatile memory product, which uses:
• mirrorbit technology - two data bits are stored in each storage array transistor
• eclipse Architecture - significantly improve program and erase performance
• 65nm process lithography
This device is connected to the host system through serial peripheral interface (SPI). Support traditional SPI unit serial input and output (single I / O or SiO) and optional two bit (dual I / O or DIO) and four bit (quadi / O or QIO) serial commands. This multi wide interface is called SPI / O or Mio.
The eclipse architecture has a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in more efficient programming and erasure than previous generation SPI programs or erasure algorithms.
Executing code directly from flash memory is often referred to as in place execution or XIP. By using the FL-S device at a higher clock rate and using the QIO command, the instruction read transmission rate can match or * pass the traditional parallel interface, asynchronous or flash memory, while significantly reducing the signal count.
S25fl127s products provide high-density products, as well as the flexibility and * * performance required by various embedded applications. It is ideal for code shadowing, XIP, and data storage.
features
• CMOS 3.0V core
• density
– 128 megabytes (16 megabytes)
• serial peripheral interface (SPI) with multiple i/o
– SPI clock polarity and phase modes 0 and 3
– extended addressing: 24 bit or 32-bit address options
– serial command sets and footprints are compatible with
S25FL-A，
S25fl-k and s25fl-p SPI series
– multiple I / O command sets and footprints are compatible with
S25fl-p SPI series
read command
– normal, * *, two-way, four-way
– auto start - power up or reset and perform normal or
Automatic quaternion read command at preselected position
address
– CFI data information for configuration.
• programming (0.8 Mbytes / s)
– 256 byte or 512 byte page programming buffer option
– four input page programming (QPP) for slow clock
system
– automatic ECC internal hardware error correction code single bit error correction generation
• erase (0.5 Mbytes / s)
– mixed sector size option - sixteen 4-kbyte physical set address space * or bottom sectors, including all remaining 64 kb sectors
– unified sector option - always erase 256 KB blocks
Software compatibility with * high density and future
Equipment.
• bicycle endurance
– at least 100000 program erase cycles per sector
• data retention
– data retention period of at least 20 years
• safety features
– 1024 byte one time program (OTP) array
– block protection:
– status register bits, used to control the protection against faults
Programming or erasing of continuous sector ranges.
– hardware and software control options
– * * sector protection (ASP)
– single sector protection by boot code or
password
cypress using eclipse's 65 nm mirror bit technology architecture
• power supply voltage: 2.7V to 3.6V
temperature range:
– Industrial (- 40 ° C to + 85 ° C)
– industrial temperature rise (- 40 ° C to + 105 ° C)
– automotive aec-q100 class 3 (- 40 ° C to + 85 ° C)
– automotive aec-q100 class 2 (- 40 ° C to + 105 ° C)
• packaging (all lead-free)
– 8-core SOIC (208 mils)
– 16 core SOIC (300 mils)
– 8-contact sensor on 6 x 5 mm
– bga-24 6 x 8 mm
– floor area of 5 x 5 balls (fab024) and 4 x 6 balls (fac024)
Option
– known good molds and known test molds